MPEG-4 Technology

MP4 Technology

MPEG-4 is a standard used primarily to compress audio and visual (AV) digital data. Introduced in late 1998, it is the designation for a group of audio and video coding standards and related technology agreed upon by the ISO/IEC Moving Picture Experts Group (MPEG) under the formal standard ISO/IEC 14496. The uses for the MPEG-4 standard are web (streaming media) and CD distribution, conversation (videophone), and broadcast television, all of which benefit from compressing the AV stream.

MPEG-4 absorbs many of the features of MPEG-1 an

d MPEG-2 and other related standards, adding new features such as (extended) VRML support for 3D rendering, object-oriented composite files (including audio, video and VRML objects), support for externally-specified Digital Rights Management and various types of interactivity. AAC (Advanced Audio Codec) was standardized as an adjunct to MPEG-2 (as Part 7) before MPEG-4 was issued.

MPEG-4 is still a developing standard and is divided into a number of parts. Unfortunately the companies promoting MPEG-4 compatibility do not always clearly state which "part" level compatibility. The key parts to be aware of are MPEG-4 part 2 (MPEG-4 SP/ASP, used by codecs such as DivX, Xvid, Nero Digital and 3ivx and by Quicktime 6) and MPEG-4 part 10 (MPEG-4 AVC/H.264, used by the x264 codec, by Nero Digital AVC, by Quicktime 7, and by next-gen DVD formats like HD DVD and Blu-ray Disc).

Most of the features included in MPEG-4 are left to individual developers to decide whether to implement them. This means that there are probably n

o complete implementations of the entire MPEG-4 set of standards. To deal with this, the standard includes the concept of "profiles" and "levels", allowing a specific set of capabilities to be defined in a manner appropriate for a subset of applications.

MPEG-4 provides a series of technologies for developers, for various service-providers and for end users.

• MPEG-4 enables different developers to create objects possessing better abilities of adaptability and flexibility to improve the qualit y of such services and technologies as digital television, animation graphics, World Wide Web and their extensions. This standard enables developers to control their content better and to fight more effectively against copyright violations.

• Various network providers can use MPEG-4 for data transparency. With the help of standard procedures such data can be interpreted and transformed into various signals compatible with any available network.

• The MPEG-4 format provides the end users with a wide range of interaction with various animated objects.

• Standardized Digital Rights Management signaling, otherwise known in the MPEG community as Intellectual Property Management and Protection (IPMP).

The MPEG-4 format can perform various functions, among which might be the following:

• Multiplexes and synchronizes data, associated with media objects, in such a way that they could be transported further via network channels.

• Interaction with the audio-visual scene, which is formed on the side of the receiver.

MPEG-4 parts

MPEG-4 consists of several standards—termed "parts"—including the following:

• Part 1 (ISO/IEC 14496-1): Systems: Describes synchronization and multiplexing of video and audio. For example Transport stream.
• Part 2 (ISO/IEC 14496-2): Visual: A compression codec for visual data (video, still textures, synthetic images, etc.). One of the many "profiles" in Part 2 is the Advanced Simple Profile (ASP).
• Part 3 (ISO/IEC 14496-3): Audio: A set of compression codecs for perceptual coding of audio signals, including some variations of Advanced Audio Coding (AAC) as well as other audio/speech coding tools.
• Part 4 (ISO/IEC 14496-4): Conformance: Describes procedures for testing conformance to other parts of the standard.
• Part 5 (ISO/IEC 14496-5): Reference Software: Provides software for demonstrating and clarifying the other parts of the standard.
• Part 6 (ISO/IEC 14496-6): Delivery Multimedia Integration Framework (DMIF).
• Part 7 (ISO/IEC 14496-7): Optimized Reference Software: Provides examples of how to make improved implementations (e.g., in relation to Part 5).
• Part 8 (ISO/IEC 14496-8): Carriage on IP networks: Specifies a method to carry MPEG-4 content on IP networks.
• Part 9 (ISO/IEC 14496-9): Reference Hardware: Provides hardware designs for demonstrating how to implement the other parts of the standard.
• Part 10 (ISO/IEC 14496-10): Advanced Video Coding (AVC): A codec for video signals which is technically identical to the ITU-T H.264 standard.
• Part 11 (ISO/IEC 14496-11): Scene description and Application engine, also called BIFS; can be used for rich, interactive content with multiple profiles, including 2D and 3D versions.
• Part 12 (ISO/IEC 14496-12): ISO Base Media File Format: A file format for storing media content.
• Part 13 (ISO/IEC 14496-13): Intellectual Property Management and Protection (IPMP) Extensions.
• Part 14 (ISO/IEC 14496-14): MPEG-4 File Format: The designated container file format for MPEG-4 content, which is based on Part 12.
• Part 15 (ISO/IEC 14496-15): AVC File Format: For storage of Part 10 video based on Part 12.
• Part 16 (ISO/IEC 14496-16): Animation Framework eXtension (AFX).
• Part 17 (ISO/IEC 14496-17): Timed Text subtitle format.
• Part 18 (ISO/IEC 14496-18): Font Compression and Streaming (for OpenType fonts).
• Part 19 (ISO/IEC 14496-19): Synthesized Texture Stream.
• Part 20 (ISO/IEC 14496-20): Lightweight Scene Representation (LASeR).
• Part 21 (ISO/IEC 14496-21): MPEG-J Graphical Framework eXtension (GFX) (not yet finished - at "FCD" stage in July 2005, FDIS January 2006).
• Part 22 (ISO/IEC 14496-22): Open Font Format Specification (OFFS) based on OpenType (not yet finished - reached "CD" stage in July 2005)
• Part 23 (ISO/IEC 14496-23): Symbolic Music Representation (SMR) (not yet finished - reached "FCD" stage in October 2006)

Profiles are also defined within the individual "parts", so an implementation of a part is ordinarily not an implementation of an entire part.

MPEG-1, MPEG-2, MPEG-7 and MPEG-21 are other suites of MPEG standards.

HyperTransport Technology

TRANSFER SPEED VERY FAST UP TO 8Gb/s

HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point-to-point link that was introduced on April 2, 2001.^[1] The HyperTransport Consortium is in charge of promoting and developing HyperTransport technology. The technology is used by AMD and Transmeta in x86 processors, PMC-Sierra, Broadcom, and Raza Microelectronics in MIPS microprocessors, AMD, NVIDIA, VIA and SiS in PC chipsets, HP, Sun Microsystems, IBM, and Flextronics in servers, Cray, Newisys, QLogic, and XtremeData, Inc. in high performance computing, and Cisco Systems in routers.

HyperTransport comes in three versions — 1.0, 2.0, and 3.0 — which run from 200 MHz to 2.6 GHz (compared to PCI at either 33 or 66 MHz). It is also a DDR or "Double Data Rate" connection, meaning it sends data on both the rising and falling edges of the clock signal. This allows for a maximum data rate of 5200 MTransfers/s when running at 2.6 GHz; this frequency is auto-negotiated.

HyperTransport supports an auto-negotiated bit width, based on two 2-bit lines to 32-bit lines. The full-sized, full-speed, 32-bit interconnect in each direction has a transfer rate of 20.8 GByte/s (2.6 GHz * (32 bits / 8)), aggregating 41.6 GB/s bandwidth in two directions, making it much faster than many existing standards. Links of various widths can be mixed together into a single application (for example, 2x8 instead of 1x16), which allows for higher speed interconnects between main memory and the CPU, and lower speed interconnects among peripherals as appropriate. The technology also has much lower latency than other solutions.

HyperTransport is packet-based, with each packet always consisting of a set of 32-bit words, regardless of the physical width of the connection. The first word in a packet is always a command word. If a packet contains an address, then the last 8 bits of the command word are chained with the next 32-bit word in order to make a 40-bit address. An additional 32-bit control packet is allowed to be prepended when 64-bit addressing is required. The remaining 32-bit words in a packet are the data payload. Transfers are always padded to a multiple of 32 bits, regardless of their actual length.

HyperTransport packets enter the interconnect in segments known as bit times. The number of bit times that it necessitates depends on the width of the interconnect. HyperTransport can be used for generating system management messages, signaling interrupts, issuing probes to adjacent devices or processors, and general I/O and data transactions. There are usually two different kinds of write commands that can be used - posted and non-posted. Posted writes are ones that do not require a response from the target. This is usually used for high bandwidth devices such as Uniform Memory Access traffic or Direct memory access transfers. Non-posted writes require a response from the receiver in the form of a "target done". Reads also cause the receiver to generate a read response.

HyperTransport also facilitates power management as it is compliant with the Advanced Configuration and Power Interface specification. This means that changes in processor sleep states (C states) can signal changes in device states (D states), e.g. powering off disks when the CPU goes to sleep.

Electrically, HyperTransport is similar to Low Voltage Differential Signaling (LVDS) operating at 2.5V.

There has been marketing confusion between the use of HT referring to HyperTransport and the use of HT to refer to Intel's Hyper-Threading feature of some Pentium 4 based microprocessors. Hyper-Threading is officially known as Hyper-Threading Technology (HTT) or HT-Technology. Because of this potential for confusion, the HyperTransport Consortium always uses the written out form: "HyperTransport".

Applications for HyperTransport

Front-Side Bus Replacement

The primary use for HyperTransport is to replace the front-side bus, which is currently different for every type of machine. For instance, a Pentium cannot be plugged into a PCI bus. In order to expand the system, the front-side bus must connect through adaptors for the various standard buses, like AGP or PCI. These are typically included in the respective controller functions, namely the northbridge and southbridge.

In theory, a similar computer implemented with HyperTransport is faster and more flexible. A single PCI↔HyperTransport adaptor chip will work with any HyperTransport enabled microprocessor and allow the use of PCI cards with these processors. For example, the NVIDIA nForce chipset uses HyperTransport to connect its north and south bridges.

Multiprocessor interconnect

Another use for HyperTransport is as an interconnect for NUMA multiprocessor computers. AMD uses HyperTransport with a proprietary cache coherency extension as part of their Direct Connect Architecture in their Opteron and Athlon 64 FX (Dual Socket Direct Connect (DSDC) Architecture) line of processors. The HORUS interconnect from Newisys extends this concept to larger clusters.

Router or Switch Bus Replacement

HyperTransport can also be used as a bus in routers and switches. Routers and switches have multiple network interfaces and data has to be forwarded between these ports as fast as possible e.g. a four port 100 MBit/s Ethernet router needs a maximum 800 MBit/s of internal bandwidth (100 MBit/s * 4 ports * 2 directions). HyperTransport greatly exceeds the bandwidth needed for this application. However, HyperTransport has largely fallen out of favour with the networking community, in favour of SPI 4.2 and PCI Express.

HTX and Co-processor interconnect

The issue of bandwidth between CPUs and co-processors has usually been the major stumbling block to their practical implementation. After years without an officially recognized one, a connector designed for such expansion using a HyperTransport interface was introduced and is known as HyperTransport eXpansion (HTX). Using the same mechanical connector as a 16-lane PCI-Express slot (plus an x1 connector for power pins), HTX allows plug-in cards to be developed which support direct access to a CPU and DMA access to the system RAM. The initial card for this slot was the QLogic InfiniPath InfiniBand HCA. Recently, co-processors such as FPGAs have appeared which can access the HyperTransport bus and become first-class citizens on the motherboard. Current generation FPGAs from both of the main manufacturers (Altera and Xilinx) can directly support the HyperTransport interface and have IP Cores available. Companies such as XtremeData, Inc. take these FPGAs (Altera in this example) and create a module that allows FPGAs to be plugged directly into the Opteron socket.

The current HTX standard is limited to 16 bits and 800 MHz, making it slower than the PCI-E standard from which it borrows its connector. An earlier Samtec test connector, however, achieved full 32-bit, 2.8GHz operation.

AMD has announced an initiative named Torrenza in September 21, 2006 to further promote the usage of HyperTransport for plug-in cards and coprocessors.

AMD Chipset 2008

AMD 700 Chipset

The AMD 700 chipset series (also called as AMD 7-Series Chipsets) is a set of upcoming chipsets designed by ATI to be sold under the AMD brand and is scheduled to launch between the end of 2007 to the first half of 2008.

The existence of the chipsets was proved on October 2006 through two hardware websites in Chile and Spain which posted the leaked slides of an ATI internal event, "ATI chipset update". In the slides, ATI have shown a series of RD700 series chipset logics. Codenamed RD790, RX790, RS790 and RS740 respectively. A codenamed SB700 southbridge was also mentioned in the event. The 790X (codenamed RD780) chipset was spotted on Computex 2007, exhibited by ASUS, while the SB750 southbridge was reported by VR-Zone .

Availability

The 790FX, 790X and 770 chipsets were launched on November 19, 2007 as part of the Spider desktop performance platform, While the others will be released on the first half of 2008, including M740G, M780G and M780T chipsets.

Lineup

790FX

• Codenamed RD790, final name revealed to be "AMD 790FX chipset"
• Dual-socket (Quad FX, Dual Socket Direct Connect (DSDC) Architecture) or single AMD processor configuration
• Maximum four physical PCI-E x16 slots and discrete PCI-E x4 slot , the chipset provides a total of 42 lanes solely in the Northbridge
• HyperTransport 3.0 with support for HTX slots and PCI Express 2.0
• ATI CrossFire X
• AutoXpress
• Extreme overclocking, reported to have achieved about 420 MHz bus for overclocking an Athlon 64 FX-62 processor , from originally 200 MHz.
• Discrete chipset cache memory of at least 16 KB to reduce the latencies and increase the bandwidth
• Supports Dual Gigabit Ethernet, and teaming option
• Reference board codenamed "Wahoo" for dual-processor system reference design board with three physical PCI-E x16 slots, and "HammerHead" for single-socket system reference design board with four physical PCI-E x16 slots, also notable was the reference boards includes two ATA ports and only four SATA 3.0 Gbit/s ports (as being paired with SB600 southbridge), but the final product with SB700 or SB750 southbridge should support up to six SATA ports
• Energy efficient Northbridge design
• Enthusiast discrete multi-graphics segment

790X

• Codenamed RD780, final name revealed to be "AMD 790X chipset" ^[9]
• Single AMD processor configuration
• Two physical PCI-E x16 slots
• HyperTransport 3.0 and PCI Express 2.0
• ATI CrossFire
• AutoXpress
• Energy efficient Northbridge design
• Performance discrete multi-graphics segment

780G/780V

• Codenamed RS780, value version codenamed RS780C
• Single AMD processor configuration
• Integrated graphics
• For 780G chipset, the implementation of side-port memory as local frame buffer was retained, as implemented in the M690T chipset , supporting DDR2 and GDDR3 modules.
• One physical PCI-E x16 slot
• HyperTransport 3.0 and PCI Express 2.0
• "Remote IT" (temporary name)
• Pin-to-Pin compatible to RS690
• Reference board design codenamed "Seahorse"
• Mobile version (M780G, codenamed RS780M) demonstrated in May 2007 , and will be available during second or third quarter (Q2-Q3) 2008 , with the implementation of PowerXpress technology, providing one PCI-E slot for AXIOM/MXM modules and HyperFlash ^[16][17] support for the Puma platform
• Energy efficient Northbridge design
• Mainstream DirectX 10 IGP segment (780G), value DirectX 10 IGP segment (780V)

770

• Codenamed RX780 , final product name revealed by ECS
• Single AMD processor configuration
• One physical PCI-E x16 slot
• HyperTransport 3.0 and PCI Express 2.0
• AutoXpress
• Pin-to-Pin compatible to RX690
• Mobile version (M780T), supports discrete graphics, and support for "add-on" graphics solution, via external PCI-E cabling
• Energy efficient Northbridge design
• Mainstream discrete single-graphics segment

740G/740V

• Codenamed RS740, value version codenamed RS740C
• Single AMD processor configuration
• Integrated graphics
• For 740G chipset, the implementation of side-port memory as local frame buffer was retained, as implemented in the M690T chipset, supporting DDR2 and GDDR3 modules.
• One physical PCI-E x16 slot and one PCI-E x4 slot
• HyperTransport 1.0 and PCI Express 1.0a
• Pin-to-Pin compatible to RS690C, to be release in late 2007
• Mobile version (M740G, codenamed RS740M) available
• Energy efficient Northbridge design
• Value DirectX 9.0 IGP segment

740

• Codenamed RX740
• Single AMD processor configuration
• One physical PCI-E x16 slot
• HyperTransport 1.0 and PCI Express 1.0a
• Energy efficient Northbridge design
• Value discrete single-graphics segment

ATI Radeon R300

Radeon R300 the third generation of Radeon graphics Chips

The Radeon R300 (introduced August 2002) is the third generation of Radeon graphics chips from ATI Technologies. The line features 3D acceleration based upon Direct3D 9.0 and OpenGL 2.x, a major improvement in features and performance compared to the preceding Radeon R200 design. R300 was the world's first fully Direct3D 9-capable consumer graphics chip. The processors also include 2D GUI acceleration, video acceleration, and multiple display outputs. "R300" refers to the development codename of the initially released GPU of the generation. R300 and its derivatives would form the basis for ATI's consumer and professional product lines for over 3 years.

The integrated graphics processor based upon R300 is called Xpress 200.

Performance

Radeon 9700's advanced architecture was very efficient and, of course, more powerful compared to its older peers of 2002. Under normal conditions it beat the GeForce4 Ti 4600, the previous top-end card, by 15-20%. However, when anti-aliasing (AA) and/or anisotropic filtering (AF) were enabled it would beat the Ti 4600 by anywhere from 40-100%. At the time, this was quite astonishing, and resulted in the widespread acceptance of AA and AF as critical, truly usable features.

Besides advanced architecture, reviewers also took note of ATI's change in strategy. The 9700 would be the second of ATI's chips (after the 8500) to be shipped to third-party manufacturers instead of ATI producing all of its graphics cards (ATI would still produce cards off of its highest-end chips). This freed up engineering resources that were channelled towards driver improvements, and the 9700 performed phenomenally well at launch because of this.

The performance and quality increases offered by the R300 GPU is considered to be one of the greatest in the history of 3D graphics, alongside the achievements GeForce 256 and Voodoo Graphics. Furthermore, NVIDIA’s response in the form of the GeForce FX 5800 was both late to market and somewhat unimpressive, especially when pixel shading was used. R300 would become one of the GPUs with the longest useful lifetime in history, allowing playable performance in new games at least 3 years after its launch.

New interface

A few months later, the 9500 and 9500 PRO were launched. The 9500 PRO had half the memory bus width of the 9700 PRO, and the 9500 "non pro" was also missing (disabled) half the pixel processing units and the hierarchical Z-buffer optimization unit (part of HyperZ III). With its full 8 pipelines and efficient architecture, the 9500 PRO outperformed all of NVIDIA’s products (save the Ti 4600). Meanwhile, the 9500 also became popular because it could in some cases be modified into the much more powerful 9700 non-PRO (np). ATI only intended for the 9500 series to be a temporary solution to fill the gap for the 2002 Christmas season, prior to the release of the 9600. Since all of the "R300" chips were based on the same physical die, ATI's margins on 9500 products were low. Radeon 9500 was one of the shortest-lived product of ATI, later replaced by the Radeon 9600 series. The logo and box package of the 9500 was "resurrected" in 2004 to market the unrelated and slower Radeon 9550 (which is a derivative of the 9600).

Also in 2004, ATI released the Radeon X300 and X600 boards. These were based on the "RV370" and "RV380" GPU respectively. They were nearly identical to the chips used in Radeon 9550 and 9600, only differing in that they were native PCI Express offerings. These were very popular for Dell and other OEM companies to sell in various configurations; connectors: DVI vs. DMS-59, card height: full-height vs. half-height.

info : wikipedia